Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships, we have established leading end-to-end capabilities and strengths across the carrier networks, enterprise, consumer, and cloud computing fields. Our products and solutions have been deployed in over 170 countries serving more than one third of the world’s population.
With 20+ sites across Europe and 1500 researchers, Huawei’s European Research Institute (ERI) oversees fundamental and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. Huawei’s ERI includes the new Zurich Research Center (ZRC), located in Zurich, Switzerland. A major element of ZRC is a new research laboratory focused on fundamental research in the area of computing systems (new hardware, new software, and new algorithms).
The research work of the lab will be carried out for leading experts in the technological area of computing with a strong reputation as academic research partners in universities across the world or in recognized global industries. Zurich Research Center provides and “open research environment” where academics and experts will be encouraged to visit and work on fundamental long-term research alongside Huawei staff in an environment that, like the best universities and research institutes, is open and conducive to such scientific work.
For our Wireless Research Lab in Zurich, we are looking for a high caliber:
Research Engineer - Computing Architecture Co-Design
Research and innovation on computing architecture and key technologies for wireless applications, i.e. high throughput algorithms, real-time/low-latency processing etc. Different solutions, e.g. SRAM based processing-in/near-memory architecture, programmable/reconfigurable architecture, SoC architecture co-design etc., should be studied to meet the requirements of intensive bitwise computing with significant data movement, deterministic latency, on-demand flexibility, energy and area efficiency.
Analyse and design a low latency data processing unit: you will be responsible for the analysis, understanding algorithm’s access patterns to provide an efficient design, and simulation that guarantees suitable data preparation before triggering the computation. You will be in charge of technical breakthroughs in key modules of the system and explore new technology.
Smart parallelism and pipelining scheme suitable to different coding and decoding algorithms, in order to improve PPA requirements for different applications including multiple scenarios.
Communicate and coordinate with line manager: As a Computing Architecture Engineer, you will be managing the communication and alignment with line manager. This includes business alignment, technical communication, and results report.
Minimum education and experience requirements
- PhD degree or equivalent in Computer Science or Electrical Engineering is required.
- At least 3 years of experience in a similar role, either in industry or in academia
- Solid background in Computer Science, baseband coding and decoding or equivalent;
- Excellent programming skills in Python/C++, systemC library is a plus;
- Ability to quickly understand a new technology area;
- Extensive experience in both algorithm and corresponding implementation, especially in baseband coding and decoding algorithms ;
- 5G, MIMO, Beamforming, Channel estimation, OFDM, modulation/demodulation, receiver, channel coding, Message Passing Algorithm;
Other skills and capabilities
- Excellent written and oral communication skills
- Strong problem-solving and analytical skills
- Excellent team player: cooperative and consultative behavior; ability to work independently and as a member of various teams.