Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships, we have established leading end-to-end capabilities and strengths across the carrier networks, enterprise, consumer, and cloud computing fields. Our products and solutions have been deployed in over 170 countries serving more than one third of the world’s population.

With 28+ sites across Europe and 2000 researchers, Huawei’s European Research Institute (ERI) oversees fundamental and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. Huawei’s ERI includes the new Zurich Research Center (ZRC), located in Zurich, Switzerland. A major element of ZRC is a research laboratory focused on research in the area of advanced computing architectures for datacenters, architecture evolution design and strategic technical planning on computing architecture.

The research in ZRC is carried out by leading experts in the technological area of computing with a strong reputation as academic research partners in universities across the world or in recognized global industries. Zurich Research Center provides and “open research environment” where academics and experts are encouraged to visit and work on research alongside Huawei staff in an environment that, like the best universities and research institutes, is open and conducive to such scientific work.

Our primary mission is driving new research and innovation to achieve breakthroughs.

We are looking for highly talented Senior Researchers for our new Computing Architecture Lab.

Responsibilities

• Explore new computing workloads, accelerate services, and improve performance in this scenario, improve and give full play to the system computing power of next-generation chips, and build the core competitiveness of the computing power base.
• Lead at least one of the following technological breakthroughs:

XPU microarchitecture innovation research

• Be responsible for chip technology planning, SoC architecture innovation and design, and participate in the end-to-end chip R&D process.
• Identify the latest technology trends and key technologies in the processor microarchitecture field, explore and innovate technical breakpoint at the SoC level.
• Participate in the discussion and communication with global customers, capture the latest microarchitecture evolution and processor chip technology trends in the industry in a timely manner, and be responsible for the technology layout in the processor domain.

Requirements

• PhD or MSc in computer science or area related to computer architecture, or equivalent research experience in industry
• At least 3 years of relevant research experience in industry or academia
• Proficiency in at least 3 of the following domains: processor microarchitecture, accelerator technology, and software and hardware collaborative performance optimization:
  1. Processor microarchitecture: extensive experience in processor microarchitecture research and end-to-end development and design, in-depth understanding of processor SoC, familiar with chip technologies such as core, cache, NoC, and memory, and leading processor SoC design, feature design, and IP development are preferred.
  2. Accelerator technologies: deep understanding of accelerator technologies and strong experience in innovation, design, and development of coprocessor design, neural network accelerator, FPGA accelerator, and ASIC accelerator design. Experience in FPGA chip design and development with a computing background and proficiency in the end-to-end development process of FPGA engineering. Experience in large-scale project delivery is preferred.
  3. Software and hardware performance optimization: understand system software principles and existing mainstream acceleration technologies and ideas, and have rich experience in performance optimization, HPC/AI acceleration, software and hardware collaborative optimization, software architecture design, and productization.
• Proficient in load characteristic analysis, modeling and simulation, and performance engineering. Familiar with the chip microarchitecture, have the capability and experience of analyzing the performance of chips from top to bottom, familiar with common profiling tools and performance engineering methodologies
• Familiar with at least one software or hardware emulation tool, SystemC/Verilog programming experience, and be able to use chip verification and emulation tools to verify the design or performance of new features.
• Excellent oral and written English.