Huawei is a leading global information and communications technology (ICT) solutions provider. Through our constant dedication to customer-centric innovation and strong partnerships, we have established leading end-to-end capabilities and strengths across the carrier networks, enterprise, consumer, and cloud computing fields. Our products and solutions have been deployed in over 170 countries serving more than one third of the world’s population.

With 28 sites across Europe and 2000 researchers, Huawei’s European Research Institute (ERI) oversees fundamental and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. Huawei’s ERI includes the Zurich Research Centre (ZRC), located in Zurich, Switzerland. A major element of ZRC is a new research laboratory focused on researching the first generation of composable-native computing infrastructure with the unification of scale-up and scale-out fabrics taking center stage.

The research work of the lab will be carried out not only by Huawei’s internal research staff but also by our academic research partners in universities across Europe. The lab will provide an “open research environment” where academics will be encouraged to visit and work on fundamental long-term research alongside Huawei staff in an environment that, like the best universities and research institutes, is open and conducive to such scientific work.

In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.

Responsibilities:

• Conduct cutting-edge research to design chiplet-based systems, with a focus on enabling high-bandwidth and low-latency interconnects across chiplets.
• Investigate various aspects of system design, including:
• Topology exploration, routing algorithms, protocol and flow control design
• Chiplet placement and interposer design strategies
• Fault tolerance and redundancy for yield and reliability
• Programming models and compiler/runtime support
• Prototype and evaluate new architectural innovations, including NoC (Network-on-Chip) enhancements and memory hierarchy design.
• Contribute to long-term research strategy through technical leadership, white papers, and vision documents.
• Publish high-quality research in top-tier conferences and journals (e.g., ISCA, MICRO, HPCA, ASPLOS, etc.).

Requirements:

• PhD in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.
• Strong background in interconnection networks and computer architecture is a must.
• Demonstrated research expertise in one or more of the following areas:
• Network-on-Chip (NoC) architecture, including routing, flow control, topologies, and performance modeling
• Packaging technologies (e.g., 2.5D/3D integration, silicon interposers)
• Programming models and hardware/software interfaces (e.g., load/store, message-passing, RDMA, shared memory models)
• System-level modeling and simulation (e.g., cycle-accurate simulators)
• Proven publication record in relevant peer-reviewed venues.
• Excellent analytical, problem-solving, and system-level thinking skills.
• Strong verbal and written communication skills, and the ability to work both independently and collaboratively in a cross-disciplinary team.